Shorties: Radiant Design Flow

Shorties: Radiant Design Flow

This Shortie demonstrates how to create a new Radiant software project, customize IP using IP Catalog, verify functionality with simulation, set timing and location constraints, process the design, analyse power consumption, analyse static timing, create on-chip debug logic.

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Shorties

Shorties

Cost: 99$
Format: Live
Date: 08.02.2021
Shorties

Shorties

Cost: 99$
Format: Live
Date: 04.05.2021
Shorties

Shorties

Cost: 99$
Format: Live
Date: 03.08.2021
Shorties

Shorties

Cost: 99$
Format: Live
Date: 04.10.2021
Shorties

Shorties

Cost: 99$
Format: Recorded
Date: 20.01.2021
Type Of Training:
Shorties
Duration:
4 hours
Participant Documents Provided:
Work Book with the presentation and Exercises
Course Objectives:

The Lattice Radiant® software is a complete toolset for designing for Lattice Semiconductor’s FPGAs. This Shortie leads you through all the basic steps of designing, constraining, implementing, and debugging designs targeted to the Lattice CrossLink-NX™ (LIFCL) device family.

This Shortie demonstrates how to:

  • Create a new Radiant software project.
  • Customize IP using IP Catalog.
  • Verify functionality with simulation.
  • Set timing and location constraints.
  • Process the design.
  • Analyse power consumption.
  • Analyse static timing.
  • Create on-chip debug logic.
Type Of Training:
Shorties
Duration:
4 hours
Participant Documents Provided:
Work Book with the presentation and Exercises
Course Objectives:

The Lattice Radiant® software is a complete toolset for designing for Lattice Semiconductor’s FPGAs. This Shortie leads you through all the basic steps of designing, constraining, implementing, and debugging designs targeted to the Lattice CrossLink-NX™ (LIFCL) device family.

This Shortie demonstrates how to:

  • Create a new Radiant software project.
  • Customize IP using IP Catalog.
  • Verify functionality with simulation.
  • Set timing and location constraints.
  • Process the design.
  • Analyse power consumption.
  • Analyse static timing.
  • Create on-chip debug logic.
Type Of Training:
Shorties
Duration:
4 hours
Participant Documents Provided:
Work Book with the presentation and Exercises
Course Objectives:

The Lattice Radiant® software is a complete toolset for designing for Lattice Semiconductor’s FPGAs. This Shortie leads you through all the basic steps of designing, constraining, implementing, and debugging designs targeted to the Lattice CrossLink-NX™ (LIFCL) device family.

This Shortie demonstrates how to:

  • Create a new Radiant software project.
  • Customize IP using IP Catalog.
  • Verify functionality with simulation.
  • Set timing and location constraints.
  • Process the design.
  • Analyse power consumption.
  • Analyse static timing.
  • Create on-chip debug logic.
Type Of Training:
Shorties
Duration:
4 hours
Participant Documents Provided:
Work Book with the presentation and Exercises
Course Objectives:

The Lattice Radiant® software is a complete toolset for designing for Lattice Semiconductor’s FPGAs. This Shortie leads you through all the basic steps of designing, constraining, implementing, and debugging designs targeted to the Lattice CrossLink-NX™ (LIFCL) device family.

This Shortie demonstrates how to:

  • Create a new Radiant software project.
  • Customize IP using IP Catalog.
  • Verify functionality with simulation.
  • Set timing and location constraints.
  • Process the design.
  • Analyse power consumption.
  • Analyse static timing.
  • Create on-chip debug logic.
Type Of Training:
Shorties
Duration:
4 hours
Participant Documents Provided:
Work Book with the presentation and Exercises
Course Objectives:

The Lattice Radiant® software is a complete toolset for designing for Lattice Semiconductor’s FPGAs. This Shortie leads you through all the basic steps of designing, constraining, implementing, and debugging designs targeted to the Lattice CrossLink-NX™ (LIFCL) device family.

This Shortie demonstrates how to:

  • Create a new Radiant software project.
  • Customize IP using IP Catalog.
  • Verify functionality with simulation.
  • Set timing and location constraints.
  • Process the design.
  • Analyse power consumption.
  • Analyse static timing.
  • Create on-chip debug logic.

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